설계검증용 소프트웨어
* High performance and High capacity Verification Environment
* 현재 사용하는 각종 Synthesis Tool, Design Entry Tool과의 호환환경 지원
* HDL Design 및 Verification을 위한 각종 Language지원
* 다양한 검증을 위한 Verification Methodology 지원
* ABV를 위한 자체 Library환경보유
* 쉽고 빠른 Debugging GUI 환경
- Full Mixed-Language Design and Verification
- TBA(TestBech Automation) and CDV Support
(SystemVerilog & SystemC)
- Assertion-Based Verification Support
- Functional Coverage Support
- Internal ABV Library Support.
- Integrated Multi-Language Debugging & analysis
- Unified Coverage database
- Power Aware Simulation Support
- LSF(Severfarm) Support
- Single kernel simulator supporting
SystemVerilog, SystemC, PSL, VHDL and Verilog
- Native-Compile architecture
- Floating license