Yield Engineering System
YES-CV200RFS
10년
주장비
시험
기계가공·시험장비 > 반도체장비 > 식각장비
2007-09-28
130,077,761원
고정형
건별
30,000원
특징
반도체 패턴 형성 후 잔류 및 기본 감광제 제거
구성및성능
▶Single wafer process ; 2", 3", 100㎜, 125㎜, 150㎜, and 200㎜
▶Dual wafer process ; 100㎜
▶Typical strip rate : 7000~8000Å/min @150℃, Max. 1.5㎛/min, <10% uniformity
▶Process Gas : O2, CF4, H2/N2
활용분야
▶Pattern Develop 후 잔류 Resist 제거
▶Etching 공정 후 Masking Layer PR 제거
◆ Process Attributes
▶ Six recipes with loop and link capability or more
▶ Single wafer process ; 2", 3", 100㎜, 125㎜, 150㎜, and 200㎜ or more
▶ Dual wafer process ; 100㎜ or more
▶ Loop process temperature feedback to prevent overheating
▶ Temperature controlled wafer hot plate for etch rate uniformity and control
▶ Typical strip rate : 7000~8000Å/min @150℃, Max. 1.5㎛/min, <10% uniformity or more
▶ Average vent N2 consumption : 0.3ft3
▶ Vent N2 process flow : 1.7SCFM
▶ Process gas flow
⇒ 0.6×10-3 SCFM @ 12SCFM pump speed rating, 150mTorr process pressure
⇒ 1.2×10-3 SCFM @ 19SCFM pump speed rating, 150mTorr process pressure
▶ Three process gases standard, forth gas option or more
▶ Up to four optional MFC's
구성및성능
▶Single wafer process ; 2" 3" 100㎜ 125㎜ 150㎜ and 200㎜
▶Dual wafer process ; 100㎜
▶Typical strip rate : 7000~8000Å/min @150℃ Max. 1.5㎛/min <10% uniformity
▶Process Gas : O2 CF4 H2/N2